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Inhalt des Dokuments

Journal Articles


S. Shivapakash and H. Jain and O. Hellwich and F. Gerfers (2021). A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. IEEE Open Journal for Circuits and Systems, 161-170.

H. Ghafarian and S. Shivapakash and S. Mortazavi and P. Scholz and N. Lotfi and F. Gerfers (2021). A 9-bit, 45mW, 0.05mm2 Source-Series-Terminated DAC Driver with Echo Canceller in 22nm CMOS for In-Vehicle Communication. IEEE Solid State Circuit Letters, 10-13.

E. Wittenhagen and M. Runge and N. Lotfi and H. Ghafarian and Y. Tian and F. Gerfers (2021). Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®. IEEE Transactions on Circuits and Systems I: Regular Papers, 57-66.


S. Wiedemann and S. Shivapakash and P. Wiedemann and D. Becking and W. Samek and F. Gerfers and T. Wiegand (2020). FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4bit-Compact Multilayer Perceptrons. ArXiV

S. Vehring and Y. Ding and P. Scholz and F. Gerfers (2020). A 3.1-dBm E-Band Truly Balanced Frequency Quadrupler in 22-nm FDSOI CMOS. IEEE Microwave and Wireless Components Letters, 1165-1168.


C. Schmidt and C. Kottke and R. Freund and F. Gerfers and V. Jungnickel (2018). Digital-to-analog converters for high-speed optical communications using frequency interleaving: impairments and characteristics. Optics Express, 6758-6770.

C. Schmidt and C. Kottke and V. Tanzil and R. Freund and V. Jungnickel and F. Gerfers (2018). Digital-to-Analog Converters Using Frequency Interleaving: Mathematical Framework and Experimental Verification. Circuits, Systems and Signal Processing, 1-26.


S. Lehmann and F. Gerfers (2017). Channel Analysis for a 6.4 Gb/s DDR5 Data Buffer Receiver Front-End. Advances in Radio Science, 157-161.

M. Schleyer and D. Maurath and H. Klar and F. Gerfers (2017). Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation. Advances in Radio Science, 49-54.


M. Schleyer and S. Leuschner, P. Baumgartner, J.-E. Müller and H. Klar (2014). An Enhanced BSIM Modeling Framework for Selfheating Aware Circuit Design. Advances in Radio Science


F. Gerfers and R. Farjad and M. Brown et al. (2012). A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. IEEE Journal of Solid-State Circuits, Invited Paper for Special Issue, 3261-3272.


F. Gerfers and P. Petkov and A. Köllmann and J. Conder and G. den Besten (2008). A 0.2-2Gbps 6xOSR Receiver using a Digitally Self-Adaptive Equalizer. IEEE Journal of Solid-State Circuits, July 2008, 1436-1448.


M. Keller and A. Buhmann and M. Ortmanns and F. Gerfers and Y. Manoli (2007). On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, June 2007, 2639-2645.


Y. Yin and H. Klar (2006). Wideband SC-Sigma-Delta Modulator Topology with Relaxed Requirement on the Integrator Settling Behaviour. WSEAS Transactions on Circuits and Systems, 499-504.


M. Ortmanns and F. Gerfers and Y. Manoli (2005). A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator. IEEE Transactions on Circuits and Systems I, Aug. 2005, 1515-1525.

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Head of Chair

Prof. Friedel Gerfers
Phone: +49 30 314-78181
Room: EN 423

Consultation hours:
by appointment only

Secretary's office Imke Weitkamp
Phone: +49 30 314-78180
Room: EN 417

Consultation hours:
Mo / Mi / Do: 14 - 16 Uhr
Di: 10 - 13 Uhr

Postal Address

Technische Universität Berlin
FG Mixed Signal Circuit Design
Sekr. EN 4
Einsteinufer 17

10587 Berlin