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Physical Design of Systems-on-Chip

3434 L 10153

Prof. Gerfers
Tobias Kaiser
Suhas Shivapakash

Integrierte LV - 2 SWS
Seminar - 2 SWS

Physical Design of Systems-on-Chip


Montag    12:00 - 14:00    Integrierte LV
Montag    14:00 - 16:00    Seminar
Beginn:    02. 11. 2020

Learning Outcomes
The students have a deep understanding of the electronics design automation principles. They can navigate modern design and verification flows for physical design of systems-on-chip. In the context of the design process, they are able to identify design challenges and problems and develop appropriate solutions to achieve design closure. The students are furthermore able to evaluate scientific research papers in this area and can derive and pursue own research approaches.

Technological advances enable growth of system-on-chip performance and complexity. In this module, students learn the concepts behind electronic design automation that enable such complex systems-on-chip, and how to create and verify standard-cell based integrated circuit layouts based on abstract HDL descriptions using modern tool flows. The module covers theoretical and practical aspects of the following topics:
- hardware design patterns
- logic synthesis
- floorplanning & placement
- clock tree synthesis
- routing
- timing analysis
- power and rail analysis

Description of Teaching and Learning Methods
This module consists of a integrated event (IV), where theoretical and practical knowledge is presented and examples are discussed. The students complete group assignments that help them in understanding and applying the topics of the integrated event (IV). In the seminar, the students are introduced to current research topics. Each of the students then pick and examine one of the topics in greater depth, write an elaboration and give a presentation about their topic.

Desirable prerequisites for participation in the courses:
Knowledge in the following areas is desired:
- Digital circuit fundamentals (logic gates, flip-flops)
- Hardware description languages such as VHDL or Verilog

Zusatzinformationen / Extras


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