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TU Berlin

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Diplom- / Master- / Bachelor - Arbeiten

Das FG Mixed Signal Circuit Design der Technischen Universität Berlin sucht motivierte Studenten, die an Diplom- / Master- / Bachelor - Arbeiten interessiert sind

Aktuelle Themen

Liste einiger Themen jetzt hier herunterladen.

Hier finden Sie Themen für Abschlussarbeiten (Studien/Bachelor- und Diplom-/Masterarbeiten), die derzeit bei uns am Fachgebiet Mikroelektronik für Studierendenangeboten werden.

Die Themen sind je nach geplantem Umgang und erforderlichem Vorwissen als Bachelor- oder Masterarbeit ausgeschrieben. Themen für eine Masterarbeit werden typischerweise aufwändigere Aufgaben enthalten, und dafür auch mehr Einarbeitung erfordern. Bei Interesse können Aufgaben und Umfang aber auch der individuellen Situation angepasst werden.

Analysis and design of a 2x time-interleaved 2GSPS Pipeline ADC in 28nm CMOS

Donnerstag, 12. Mai 2016

RF and baseband section of a typical LTE handset radio.
Lupe

Analysis and design of a 2x time-interleaved 2GSPS Pipeline ADC in 28nm CMOS

LTE and 5G Wireless Infrastructure (also known as Base-Stations) require ultra-high performance RF- & analog building blocks. 

Therefore, in this thesis the design of the Pipeline ADC  will be addressed. A more detailed description can be found below.

The  first pipeline stage are the performance critical building blocks of a pipeline ADC. The ADC input buffer drives the TH stage of the pipeline ADC, providing low output impedance to guaranty settling, minimize kickback as well as low noise. The first pipeline stage performs the actual track-and-hold functionality as well as the conversion of the first MSB bits of the pipeline ADC. Thus the noise and settling performance are critical to achieve high accuracy. 

This Master thesis will review, analyze and design a 2x time-interleaved pipeline stage operating at 2GSPS for a 4GSPS 14bit pipeline ADCThe ADC is targeting 14bits of resolution, ~70dB of SNR and 95dB HD3 at low frequency input sine wave and (if possible) 85dBFS at 1GHz -1dB full scale input signal. The target process is a 28nm GF. 

Based on findings during the design period, the upper performance metrics might be adjusted. 

Please find the pdf download here.

A High-Speed Analog-to-Digital Converter for Next-Generation Communication Devices

Mittwoch, 06. Januar 2016

Bachelor / Master Thesis

A High-Speed Analog-to-Digital Converter for Next-Generation Communication Devices

Looking at the agendas and roadmaps of communication industries as well as semiconductor technology providers suggests another performance leap of a factor 10 to 100 by 2020. This sets up a huge challenge for system architectures, algorithms, and also the underlying circuit technology for achieving tis. These requirements are very significant at the interface from the analog to the digital world, the analog-to-digital converter (ADC). It is significant on the one hand, because the ever faster and more complex analog and signal digital modulation concepts, and on the other hand, due to scaling and diversity of the semiconductor technology itself using.

The Master Thesis will aim for implementing a time-interleaved ADC in 28nm CMOS technology. The work is closely related to a funded project collaborating with partners in microwave and transceiver baseband design, which is a good chance to get holistic system understanding. The particular work on the ADC building block needs to address sampling precision, timing and gain calibration techniques, as well as circuit optimization, implementation and performance verification. Ideally, the design can be completed all the way up to layout and tape out to a semiconductor fab.

Further information...

 

 

 

Multimode Receiver including Adjustable Low-Noise Amplifier for Software-Defined Radio

Mittwoch, 06. Januar 2016

Bachelor / Master Thesis

Multimode Receiver including Adjustable Low-Noise Amplifier for Software-Defined Radio

With the trend towards versatile high performance wireless communication many communication standards and have emerged. Addressing only one standard with each device is expensive, limiting in application possibilities, and allows only low spectrum efficiency. Instead, modern receiver devices are needed which are enabled for multiple standards, such as W-CDMA and IEEE802.11a wireless LAN, and USRP B200 for wireless USB 3.0. The concept for this is software designed radio (SDR). However, it relies on the front-end mixed-signal circuit which needs to allow switching between frequency bands, channels, filter characteristics, and modulation options.

In a first stage, the Thesis aims for optimizing a 28 nm CMOS low-noise amplifier (LNA) for 70 MHz to 6 GHz with a noise figure of below 2 dBm. Further on, the amplifier needs to match to the baseband mixer for providing I/Q demodulation. Eventually, a filter and impedance matching network is to be optimized to interface the analog-to-digital converter. Alternatively, the LNA can be scaled and extended to be integrated with phase-array antenna. Optionally, a digital configuration logic can be implemented for adjustment of the baseband mixer in order to comply with the various standards including IoT wireless communication.

Further information...

 

 

A 17-GHz Clock Distribution Network and Phased-Locked Loop for W-Band Communication Applications

Mittwoch, 06. Januar 2016

Bachelor / Master Thesis

A 17-GHz Clock Distribution Network and Phased-Locked Loop for W-Band Communication Applications

Next-generation 5G communication offer tremendous improvements of wireless communication. A key enabler of such standards is inevitably the mixed-signal and microwave circuits design technology. The challenges are not only the extreme frequencies of over 100 GHz, but also the bandwidth, which multiplies challenges for impedance matching and clocking accuracy.

The Thesis will aim for a design of an integrated clock distribution network with oscillator and phased-looked loop multipliers to achieve at least 17 GHz with minimum phase noise, but plenty of power (> 10 dBm) to pump phased-array antenna front-ends, the digital baseband, and the analog-to-digital converter (ADC). This clock generating circuit can be realized fully on chip in CMOS technology, as well as on circuit board (PCB) with discrete components. The work is closely related to a funded research project collaborating with partners in microwave and transceiver front-end as well as baseband design - a good chance to get holistic system understanding, too.

The particular work starts with system design specifications, as well as device and a short market research. The clocking circuits need transmission lines with complex impedance matching and low cross talk. Frequency multiplication with minimized phase noise is crucial.

Further information...

 

 

 

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Head of Chair

Prof. Friedel Gerfers
Phone: +49 30 314-78181
Room: EN 423

Secretary's office

Imke Weitkamp
Phone: +49 30 314-78180
Room: EN 417

Postal Address

Technische Universität Berlin
FG Mixed Signal Circuit Design
Sekr. EN 4
Einsteinufer 17

10587 Berlin
Germany