Marcel Runge, MSc.
Einrichtung | Mixed Signal Circuit Design |
---|---|
Sekretariat | EN4 |
Gebäude | E-N |
Raum | E-N 420 |
Research Assistant
Lectures
Vita
Marcel Runge received the B.Sc. in 2012 and the M.Sc. in 2015 from the Leibniz Universität Hannover, Germany both in electrical engineering and information technology. During a one-year internship at the Silicon Valley, USA based startup Aquantia Corp, he contributed to the high speed TX Digital-to-Analog-Converter design for 10GBase-T data communication in 28nm. While working on his Masters thesis at the company KLA-Tencor, USA, he developed a deep understanding of CCD sensor-readout architectures to maximize the signal-to-noise ratio. Currently, he is working towards the Ph.D. degree at MSC chair.
Research Interests
- Ultra linear (>90 dB SFDR), low power continuous-time sigma delta modulators (CTSDM) with moderate bandwidths (10-50MHz)
- Background on-chip calibration routines with focus on low hardware costs
- RF digitization
- Software-defined radio receivers
Supervised Bachelor/ Master Theses
- Analysis of Process Induced Temperature Inversion in 28nm CMOS
- A High-Speed SAR ADC Logic in 28nm CMOS
- A gm-C Filter Design for Continuous-Time Sigma-Delta ADC in 28nm CMOS
Publikationen
2023
Runge,
M.;
Edler,
J.;
Kaiser,
T.;
Misselwitz,
K.;
Gerfers,
F.
An 18-MS/s 76-dB SNDR Continuous-Time ? ? Modulator Incorporating an Input Voltage Tracking GmC Loop Filter
IEEE Journal of Solid-State Circuits, 58 (8) :2288-2299
2023
An 18-MS/s 76-dB SNDR Continuous-Time ? ? Modulator Incorporating an Input Voltage Tracking GmC Loop Filter
IEEE Journal of Solid-State Circuits, 58 (8) :2288-2299
2023
2022
Runge,
M.;
Edler,
J.;
Schmock,
D.;
Kaiser,
T.;
Gerfers,
F.
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΣΔ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS
Custom Integrated Circuits Conference (CICC)
Herausgeber: IEEE
2022
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΣΔ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS
Custom Integrated Circuits Conference (CICC)
Herausgeber: IEEE
2022
2021
Runge,
M.;
Schmock,
D.;
Kaiser,
T.;
Gerfers,
F.
A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS
IEEE Custom Integrated Circuits Conference 2021
Herausgeber: IEEE
2021
A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS
IEEE Custom Integrated Circuits Conference 2021
Herausgeber: IEEE
2021
Runge,
M.;
Edler,
J.;
Kaiser,
T.;
Gerfers,
F.
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS
IEEE Custom Integrated Circuits Conference 2021
Herausgeber: IEEE
2021
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS
IEEE Custom Integrated Circuits Conference 2021
Herausgeber: IEEE
2021
Edler,
J.;
Runge,
M.;
Gerfers,
F.
A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seite 1090-1093
Herausgeber: IEEE
2021
A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seite 1090-1093
Herausgeber: IEEE
2021
Wittenhagen,
E.;
Runge,
M.;
Lotfi,
N.;
Ghafarian,
H.;
Tian,
Y.;
Gerfers,
F.
Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®
IEEE Transactions on Circuits and Systems I: Regular Papers, 68 (1) :57-66
2021
Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®
IEEE Transactions on Circuits and Systems I: Regular Papers, 68 (1) :57-66
2021
2020
Runge,
M.;
Schmock,
D.;
Wittenhagen,
E.;
Gerfers,
F.
A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX
IEEE International Symposium on Circuits and Systems (ISCAS), Seite 1-5
Herausgeber: IEEE
2020
A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX
IEEE International Symposium on Circuits and Systems (ISCAS), Seite 1-5
Herausgeber: IEEE
2020
Wittenhagen,
E.;
Runge,
M.;
Keusgen,
W.;
Gerfers,
F.
A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio
International Symposium on Circuits and Systems (ISCAS)
Herausgeber: IEEE
2020
A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio
International Symposium on Circuits and Systems (ISCAS)
Herausgeber: IEEE
2020
2019
Runge,
M.;
Lotfi,
N.;
Gerfers,
F.
Optimized Zero Placement Within Noise Coupling Transfer Functions for Oversampled ADCs
IEEE Int. Symp. on Circuits and Systems (ISCAS)
Herausgeber: IEEE
2019
Optimized Zero Placement Within Noise Coupling Transfer Functions for Oversampled ADCs
IEEE Int. Symp. on Circuits and Systems (ISCAS)
Herausgeber: IEEE
2019
Lotfi,
N.;
Ibáñez,
P. Lehmann;
Runge,
M.;
Gerfers,
F.
A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI
IEEE International Symposium on Circuits and Systems (ISCAS)
Herausgeber: IEEE
2019
A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI
IEEE International Symposium on Circuits and Systems (ISCAS)
Herausgeber: IEEE
2019
Gerfers,
F.;
Lotfi,
N.;
Wittenhagen,
E.;
Ghafarian,
H.;
Tian,
Y.;
Runge,
M.
Body Biasing Techniques in CMOS FD-SOI for Mixed-Signal and RF Designs
International Conference on Electronics Circuits and Systems (ICECS)
Herausgeber: IEEE
2019
Body Biasing Techniques in CMOS FD-SOI for Mixed-Signal and RF Designs
International Conference on Electronics Circuits and Systems (ICECS)
Herausgeber: IEEE
2019
Runge,
M.;
Gerfers,
F.
A 44fs RMS Jitter 6GHz Limiting Amplifier in 22nm CMOS FDSOI
12th German Microwave Conference 2019
Herausgeber: IEEE
2019
A 44fs RMS Jitter 6GHz Limiting Amplifier in 22nm CMOS FDSOI
12th German Microwave Conference 2019
Herausgeber: IEEE
2019
2018
Runge,
M.;
Schmock,
D.;
Scholz,
P.;
Boeck,
G.;
Gerfers,
F.
A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Seite 26-29
Herausgeber: IEEE
2018
A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Seite 26-29
Herausgeber: IEEE
2018
Lotfi,
N.;
Runge,
M.;
Gerfers,
F.
A MDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs
IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS)
Herausgeber: IEEE
2018
A MDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs
IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS)
Herausgeber: IEEE
2018
Runge,
M.;
Linnhoff,
S.;
Gerfers,
F.
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS
IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS)
Herausgeber: IEEE
2018
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS
IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS)
Herausgeber: IEEE
2018
Runge,
M.;
Gerfers,
F.
Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ΣΔ ADCs With Pseudo Random Noise
IEEE Int. Symp. on Circuits and Systems (ISCAS), Seite 1-5
Herausgeber: IEEE
2018
Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ΣΔ ADCs With Pseudo Random Noise
IEEE Int. Symp. on Circuits and Systems (ISCAS), Seite 1-5
Herausgeber: IEEE
2018
2017
Runge,
M.;
Gerfers,
F.
A Digital Compensation Method Canceling Static and Non-Linear Time-Variant Feedback DAC Errors in ΣΔ Analog-to-Digital Converters
IEEE Int. Symp. on Circuits and Systems (ISCAS), Seite 1-4
Herausgeber: IEEE
2017
A Digital Compensation Method Canceling Static and Non-Linear Time-Variant Feedback DAC Errors in ΣΔ Analog-to-Digital Converters
IEEE Int. Symp. on Circuits and Systems (ISCAS), Seite 1-4
Herausgeber: IEEE
2017
Runge,
M.;
Schmock,
D.;
Gerfers,
F.
Noise and Non-Linearity Analysis of a Charge-Injection-Cell-Based 10-bit 50-MS/s SAR-ADC
IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS), Seite 1025-1028
Herausgeber: IEEE
2017
Noise and Non-Linearity Analysis of a Charge-Injection-Cell-Based 10-bit 50-MS/s SAR-ADC
IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS), Seite 1025-1028
Herausgeber: IEEE
2017
2016
Runge,
M.;
Mathis,
W.;
Gerfers,
F.
Analysis and Modeling of Low-Noise Optical Sensor Readout Architectures
Analog Workshop 2016, Leibniz Universität Hannover
2016
Analysis and Modeling of Low-Noise Optical Sensor Readout Architectures
Analog Workshop 2016, Leibniz Universität Hannover
2016