TU Berlin

Mixed Signal Circuit DesignSuhas


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Suhas Shivapakash


Suhas Shivaprakash, M.Sc.
Research Associate
Phone: +49 30 314-78189
Room: EN438
LinkedIn: https://www.linkedin.com/in/suhas-s-50507090/


1. Low Power and Energy Efficient Deep Neural Network for Reconfigurable Machine Learning Accelerators

Deep Neural Network (DNN) is a sub-class of Artificial Neural Network (ANN), which has provided successful performance in all the cloud centric deep learning algorithms ranging from speech recognition, image recognition, and virtual art processing of the captured images.

The main motivation behind this work is the implementation of processing accelerator unit in the parallelism mode in convolution layers (CLs), recurrent layers (RLs) or on any other DNN layers with a different weighted bit precision operating at around 500MHz clock frequency with a core voltage of 0.8 to 1V in 22nm FDSOI. As it is important to achieve better energy efficiency with a low power, a novel technique of STRIPES (STR) in bit serial computation method is employed.

The application of the work is mainly in the use of new state of art architectures such as “DaDianNao – machine learning supercomputer”, face/image recognition or in other social media applications which involves the human-machine interaction.


2. 12GHz Direct Digital Synthesizer (DDS) Implementation with PAM Modulation for RF-DAC

DDS is an arbitrary frequency generator fixed with respect to the clock input (12GHz). The DDS with PAM modulation reads the data from the third party application and operates both in ROM and RAM mode. The data read will be stored in the memory and based on the value of the frequency controller the required set of data pattern are generated to the DAC, the value of the frequency controller mainly depends on the frequency at which the signals needs to be generated.


Thesis Offers

Master thesis:
Design and Implementation of a 12-bit 12 GHz Direct Digital Synthesizer in 22nm FDSOI
More info here.

Master or Bachelor thesis:
Design and Implementation of 15-bit 1GHz Decimator design for Pipeline ADC in 65nm
More info here.


Suhas received his Bachelor of Engineering degree in Electronics and Communication Engineering in 2014 and Master of Technology in VLSI Design and Embedded System in 2016 and he studied in RNSIT, affliated to Visvesvaraya Technological University and IIT Gandhinagar. His research interest mainly focused on the areas of Digital VLSI, machine learning and Neural Networks. Suhas has a previous work experience of implementing ZigBee communication module for wireless communication of spacecraft and genetic algorithm implementation on FPGAs to avoid single event upset in the spacecraft for interplanetary space exploration from ISRO Satellite Centre, Bangalore. Currently he is working under Prof. Gerfers in the area of machine-learning processor development for his PhD degree.


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